Exemplary embodiments of the present invention relate to a technology of semiconductor device fabrication, and more particularly, to a semiconductor device and a method for fabricating the same, by which a leakage current in a junction region may be reduced.
As a degree of integration of a semiconductor device increases, a channel length of a transistor decreases. Also, as the channel length of a transistor decreases, operation characteristics of the semiconductor device may be degraded.
FIG. 1 is a cross-sectional view illustrating a transistor of a conventional semiconductor device.
Describing a conventional transistor with reference to FIG. 1, a gate 17 is formed to have a structure in which a gate dielectric layer 14, a gate electrode 15 and a gate hard mask layer 16 are stacked over a substrate 11. Junction regions 12 are formed in the substrate 11 on both sides of the gate 17. Here, a region where a source or a drain of MOSFET formed is referred to as the junction region. In general, since the junction regions 12 are formed through ion implantation process after forming the gate 17, the gate 17 may overlap with portions of the junction regions 12.
In the transistor having the above-described construction, the junction regions 12 and the substrate 11 have different conductivity types. For example, in a case of an NMOS transistor, the junction regions 12 and the substrate 11 respectively have N-type conductivity and P-type conductivity, and an impurity doping concentration of the junction regions 12 is greater than that of the substrate 11. Consequently, a PN junction may be formed between the substrate 11 and the junction regions 12. Moreover, a depletion region 18 may be formed between the substrate 11 and the junction regions 12 by the PN junction.
However, as a channel length of the transistor decreases due to increase in a degree of integration of a semiconductor device, a leakage current may occur between the junction regions 12 and between the substrate 11 and the junction regions 12 due to an internal electric field of the depletion region 18 formed between the substrate 11 and the junction regions 12 even when an operating voltage is not applied to the gate 17. The leakage current due to the internal electric field of the depletion region 18 may increase as the impurity doping concentration of the junction regions 12 increases and the channel length of the transistor decreases.